• Will define Bus Protocol which is commonly referenced in Design examples. The naming is arbitrarily defined by us, so it may be replaced as per requirements.


• Similar toAXI Specification, independent channels for Request、Read Data , Write Data are in the bus specification. Each pipeline will not overlap (interfere) but connect directly.


• May remove options from bus used by us, to make it Simpler^[1]


• It is important for the bus protocol to maintain the order of request（I is possible to have Out-of-order if special rules are specified). And it is necessary to maintain Coherence^[2]. But this is beyond the scope of definition here so will explain separately.


• IO in the table is the signal I=Input and O=Output when it is operated as master signal direction. Pol is the polarity and + is positive logic and - is negative logic. Further in modules there are prefixes attached to signal names.（req → iReq）。


• Request（address）interface instructs the address and requests the memory allocation. Unit of allocation is defined beforehand between modules（Burst length is an option）.



Signal Name	IO	Pol	Explanation
req	O	+	Request signal which is not evaluated until gnt is asserted
gnt	I	+	Permit signal which acknowledges req and addr at slave side   If slave side can accept then this signal should be asserted beforehand
rxw	O	+	Represents Read/Write, asserted in sync with req
addr	O	+	Represents address, asserted in sync with req   Range is arbitrarily defined




• Read Data interface provisions handshake for data read. Request interface reads the burst of each read allocation . Will also define abort signal although it is an option as it is required for explaining design example.



Signal Name	IO	Pol	Explanation
rdStrb	O	+	Will not be evaluated until read execute signal rdAck is asserted   In case master side can receive then maybe asserted beforehand
rdAck	I	+	Signifies that read possible signal rdData is ready   Assert allocation unit with 1 Request
rdFlush	O	+	Asserted when read is aborted
rdData	I	+	Assert in sync with read data rdAck   Range is arbitrarily defined




• Write Data interface provisions handshake for write data. Request interface writes the burst of each Write allocation. Will also define abort signal although it is an option as it is required for explaining design example.



Signal name	IO	Pol	Explanantion
wrStrb	O	+	Will not be evaluated until write execute signal wrAck is asserted   Signifies wrData, wrMask are ready   Assert allocation unit with 1 Request
wrAck	I	+	Write possible signal   If slave side can receive then to assert beforehand
wrFlush	O	+	Assert when need to abort write
wrData	O	+	Assert in sync with write data wrStrb   Range is arbitrarily defined
wrMask	O	+	Assert in sync with write mask wrStrb   Byte or bit is arbitrarily defined.（Byte as much as possible）




• Wave sample（wrMask is omitted). Mixed R/W access from A to F Burst length is 4 fixed, but partially aborted using rdFlush & wrFlush signals


• In order to maintain coherence, will postulate that address is same for Read[D] followed by Write[F] and write[F] is not executed until Read[D} is completed.
  

Circuit Design > Home > Protocol used    Next page（Profile）   TOP ▲

[1]
May add in order to explain design example. If added from the start it will make things complicated and harder to understand

[2]
When Write to same address as Read from, the value has to be the same. However if the R/W pipeline is independent, then need control to check both read and write. To maintain this coherence, cost rises and therefore need to exclusive control on the master side