Information Update（2012/6/1～）

Update Date Index Content

2012.6.19 Design[FIFO] Using sample code, modified the discrepancy in pointer comparision at the time of Stall generation（FIFO all pages）

2012.7.17 Design[DDR] Created

2012.8.1 Overall Modified attachment of image folder （Diagram was invisible. corrected it）

2012.10.31 Home[Profile] Addition of N.M.

2012.10.31 Home[Language・Coding Style] FF description modification and addition of combination circuit

2012.11.5 Test[Bus slave] Created

2012.11.5 Test[SRAM Model] Created

2012.11.5 Design Example[FFT] 2 port SRAM description deleted（Specified reference）

2012.11.5 Design Example[Cache] Created

2012.11.7 Design Example[FIFO] SRAM Model changed inline description to reference

2013.2.12 Design[CIC Filter] Created

2013.2.12 Technic[Fast computation] Created(CSA addition)

2013.3.18 Design Example[DDR Control(implementation)] Created

Update Date	Index	Content
2012.6.19	Design[FIFO]	Using sample code, modified the discrepancy in pointer comparision at the time of Stall generation（FIFO all pages）
2012.7.17	Design[DDR]	Created
2012.8.1	Overall	Modified attachment of image folder （Diagram was invisible. corrected it）
2012.10.31	Home[Profile]	Addition of N.M.
2012.10.31	Home[Language・Coding Style]	FF description modification and addition of combination circuit
2012.11.5	Test[Bus slave]	Created
2012.11.5	Test[SRAM Model]	Created
2012.11.5	Design Example[FFT]	2 port SRAM description deleted（Specified reference）
2012.11.5	Design Example[Cache]	Created
2012.11.7	Design Example[FIFO]	SRAM Model changed inline description to reference
2013.2.12	Design[CIC Filter]	Created
2013.2.12	Technic[Fast computation]	Created(CSA addition)
2013.3.18	Design Example[DDR Control(implementation)]	Created