• Like an assembly line, flow has input, process, output. Normally processing is done sequentially to improve performance (parallel processing).


• In order to change the parameter or to provide feedback to an earlier stage, in order to keep coordination, it becomes necessary to stop the operation. In this case the time between input to output (Latency) becomes relevant.


• In the diagram below, Process 5 denoted with operation A in purple cannot change the common parameters till the operation finishes and operation B denoted in Skyblue cannot start. Hence the operation in dash line (white fill) needs to be voided. Multipurpose processors have such dependency situations occur regularly and in order to resolve these, various technics are employed making these processors expensive.


• Pipeline can be used for improved speed and reduction of circuit by circuit slicing. The below diagram shows 32 bit multiplication separated into 2 steps α, β realizing improved performance and reduction of circuit^[2]できることを示しています。


• Multiple pipelines aregroupedaccording to rule. Further by regrouping, different functions can be implemented. By wisely reusing the pipeline, system can also be implemented comparatively easily

• Pipeline basically consists of only input and output, so that by grouping required functions, can achieve what is required. By experiencing the basics, applications and implementations of pipeline and getting well acquainted with the concepts, it is possible to visualize image of circuit intuitively.


• Looks as if the design is bottom up with combining basic functions but need to design top down keeping the performance and cost in balance For instance, see the below
  • As much as possible to breakdown to reusable unit, and finally to basic elements
  
  
  • Fix smallest throughput which can be the performance target
  
  
  • For each element, smallest throughput to be required condition, thereby reducing the circuit size. Bythroughput control if the intermediate rtio changes, then to design using that ratio
  
  
  • Due to ArbitrationorResource Sharingif a bubble cycle occurs, then need to think either to prioritize cost so that throughput is reduced or to prioritize performance
  
  
• To design an individual pipeline is sinple. However to share memory or high costpipeline resourcesor to compress parameters division of pipeline or combination of pipeline are required. Most bugs can enter the pipeline at combination. Even with careful verification can still miss bugs so need to take extreme care and check the source.


• operating frequency is determined by physical elements as well as logical steps. Designer can only take part in designing structure whch is the logical steps for each element of the pipeline


• pipeline elementsStagecontrol unit or interface specification is fixed at system or organization level and readability or reuseability is increased


• Pipelineparallelizes on a time axis^[3]smallest required function so it provides excellent cost performance. On the other hand, parallelization on stage unit is required. Cost will increase according to the parallelization units. Parallelization also is needed when there is send/receive over the system as in memory. In that case dropping frequency or processing data in time division are ways having merits (circuit reduction) or demerits (complexity or extendability) and both these need to be considered.


• When bubble cycle occurs, it is difficult to resurrect the lost data, hence try to avoid as much as possible. For instance, when stopping the flow of the pipeline in order to synchronize the pipeline, try to adjust the length of the pipeline as well as mediateto absorb random flickers through FIFO and average them.


• Input throughput and output throughput have individual flickers, hence final check on whether both their flickers are absorbed by the pipeline or not needs to be performed.（ Buffer type（S₂）jointやFIFOis used.）。When avrage flow capacity of input flow and output flow is fixed, and complete absorption is possible, then logically it is possible to obtain throughput of either of the lesser flow. However when cannot absorb at all, both input and output are acted upon and the product of average flow capacity can only be obtained. When average flow capacity of input/output is 50% and 40% respectively, for the former it will be min of (50%, 40%) which is 40%、and for the latter will be the product of 50%ｘ40% which is 200%.


• Structure taking into account the pipeline, makes it easy to highly clock gating the pipeline entirely or each of its independent stages. It is also easier to compute the circuit size of the total, and balanced low power consumption can be implemented.

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[1]
Here manage in one unit summation of pipeline function. By combining these, would like to provide a high level module.

This is out design style. Does not mean that this is the correct style and we try to think of improving where necessary.

[2]
For example, when performing 32bit multiplication in 1 cycle, requires more than 50 logical stages depending on the cell library. It is how these 50 stages can be viewed, but personally think that from experience it is quite a lot.

If latency is not as important then can divide into 16 bits and can reduce the stages to a few stages instead of 50. Basically circuits with more logical stages require high cost cells at the time of logical synthesis and the circuit size also tends to increase.

[3]
For example, RGB of image is commonly word packed into 32bit, and when it is parallely processed in this unit then pipeline structure becomes simple.

On the other hand, when RGB is divided into each element ( Planer）, then cost can be reduced if only each element alone is processed. However processing different combination of elements will be difficult due to sychronization.

The former is simple and better from the perspective of circuit quality. For cost reduction, it is also a mthod whereby RGB are packed as well as processed alternately.